The present disclosure relates to fault-tolerant memory in integrated electronic circuits, and more specifically, to systems and methods to redirect virtual addresses for replacing defective elements of variable size in memory devices.
A memory chip with even a single failed array cannot be sold, which significantly degrades product yield. A known solution is to provide spare arrays to replace the failed ones. There are two problems with this solution. First, as memory size grows, the cost of providing a spare memory array increases and the effectiveness decreases; for 3-D stacked memories, a spare memory array will not suffice. Second, a spare memory array is almost entirely useless in recovering from memory architecture faults (e.g. faults in the address and data buses); for 3-D memories, faults in the 3-D interconnect are a serious risk, so a circuit that can repair these faults is needed.